For the purposes of the present invention, the expression “metal oxide semiconductor field-effect transistors” (MOSFET) denotes various field-effect transistor structures, each including a wafer of semiconductor material, also called the substrate or body, a drain region and a source region integrated in the wafer, and a gate structure including a layer of conductive material separated from the wafer by a layer of insulating material (typically an oxide, such as silicon dioxide). It should be noted that the expression “metal oxide semiconductor” (MOS) is also used for transistors in which the layer of conductive material of the gate is formed by a layer of doped polysilicon, instead of metal. It should also be mentioned that metal oxide semiconductor transistors are also called insulated-gate field-effect transistors (IGFET, insulated-gate FET), to emphasize that the gate electrode is electrically insulated from the wafer or body.
For example, for the purposes of the present invention the term MOSFET is applied not only to transistors having the standard structure, such as the conventional NMOS and PMOS transistors, but also lateral double-diffusion MOSFETs (LDDMOSFET or LDMOSFET), or other possible MOSFET structures comprising a different number of diffused regions and/or a different arrangement thereof in the substrate, as well as different combinations of the dopants. It is known that an LDMOSFET, referred to for brevity below as an LDMOS transistor, comprises, in addition to the drain and gate regions, a body region which is also diffused under the gate oxide and a drift region associated with the drain.
As is known, one of the parameters characterizing a MOSFET is the breakdown voltage BV. With reference to LDMOS transistors for example, the breakdown voltage BV is the voltage of the drain electrode at which the junction between the drain and body is subject to an avalanche effect (avalanche breakdown). The breakdown voltage BV is correlated with the dopants of the drain (or drift) and body regions and with the curvature and denser spacing of the lines of potential induced by the gate electrode. In the known art, two different methods are used to obtain sufficiently high values of breakdown voltage (BV) in MOS or LDMOS transistors.
In the first method, the doping of the drain and body regions is appropriately determined, and, in particular, the doping of the drain region is reduced. This method has the disadvantage of decreasing the performance of the transistor, causing an increase in its series resistance (Ron). The second conventional method proposes the use of a relatively thick gate oxide layer. This approach has the disadvantage of reducing the transconductance Gm and the current-carrying capacity of the LDMOS transistor, thus decreasing the performance of the transistor in terms of gain.
In the known art, therefore, in the case of LDMOS transistors, the doping and thickness of the gate oxide must be determined in such a way as to provide a compromise between the requirements of a suitable breakdown voltage, a convenient gain and an adequate series resistance, and this compromise cannot be considered to be wholly satisfactory.